The storage density of a semiconductor memory device as represented by a DRAM (Dynamic Random Access Memory) is increasing in recent years, and a high speed is also required. The increase of the storage density has so far been achieved mainly by downsizing of memory cells and increase of chip sizes. However, there is a certain physical limit to a reduction in the size of the memory cell, and the increase in the chip size decreases productivity and hinders a speed increase.
In order to substantially solve the above problems, there is proposed a method of using separate chips for the core section that is formed with memory cells and the interface section that is formed with a peripheral circuit of the memory cells (see Japanese Patent Application Laid-open No. 2004-327474). According to this method, a semiconductor memory device that has conventionally one chip is divided into plural chips. Therefore, the size of one chip can be decreased substantially. Consequently, according to this method, it is expected to be able to achieve a larger density while securing high productivity.
When the core section and the interface section are formed using separate chips, core chips can be manufactured in the memory process, and the interface chips can be manufactured in the logic process. In general, a transistor manufactured in the logic process can achieve higher-speed operation than a transistor manufactured in the memory process. Therefore, when the interface chip is manufactured in the logic process, the circuit of the interface chip section can be operated at a higher speed than that conventionally achieved. Accordingly, the semiconductor memory device can achieve high-speed operations. Furthermore, the operation voltage of the interface chip can be decreased to about 1V, thereby decreasing power consumption.
However, when the core chip is a DRAM, it is difficult to greatly decrease the operation voltage. Therefore, when the power supply terminal of the core chip is made common to the power supply terminal of the interface chip, an optimum voltage cannot be given to each chip. When the power supply terminal is made common, there is a risk of damaging the interface chip in the stress test (burn-in test). In other words, in the burn-in test, a high stress needs to be given to the memory cells, by applying a higher voltage than that usually used. However, when this high voltage is also applied to the interface chip, the transistor within the interface chip having a low withstand voltage has a risk of being broken.
Various methods of applying different voltages to the core section and the interface section within the same chip are conventionally proposed (see Japanese Patent Application Laid-open Nos. 2004-152399, 2003-218210, 2003-208800, H6-203600, H6-55324, and S58-114392).
According to these methods, a power supply pad for supplying an operation voltage to the core section and a power supply pad for supplying an operation voltage to the interface section are provided separately. However, when the core section and the interface section use different chips, the power supply pads for the respective chips are provided separately. Therefore, a connection path for connecting each power supply pad to an external terminal is necessary, unlike the configuration of the usual semiconductor memory device having one chip.
On the other hand, when the core chip and the interface chip are applied with mutually different voltages, the amplitude of the signal within the core chip is different from the amplitude of the signal within the interface chip. Therefore, there is a risk of the occurrence of a trouble in exchanging a signal between these chips. This problem is serious in the burn-in test. When a high-voltage signal is output from the core chip to the interface chip, there has been a risk that transistors in the input circuit of the interface chip are latched up, thereby breaking the interface chip.